Device with 3D inductor and magnetic core in substrate

ABSTRACT

Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application for patent claims the benefit of ProvisionalPatent Application No. 62/908,450 entitled “DEVICE WITH 3D INDUCTOR ANDMAGNETIC CORE IN SUBSTRATE” filed Sep. 30, 2019, and assigned to theassignee hereof and hereby expressly incorporated herein by reference inits entirety.

FIELD OF DISCLOSURE

This disclosure relates generally to devices, such as integrated passivedevices (IPD) formed on a substrate, and more specifically, but notexclusively, to a device with a three dimensional (3D) inductor having amagnetic core embedded in the substrate.

BACKGROUND

Integrated circuit technology has achieved great strides in advancingcomputing power through miniaturization of active components. Integratedpassive components have also been miniaturized. As frequencies and datarates get higher, there is a need for further miniaturization ofintegrated passive components, for example, filters which includeinductive (L) and capacitive (C) elements in integrated circuit device.Additionally, to improve quality of received signals, certain componentsof a mobile device may be formed on an insulating substrate (e.g., glasssubstrate). For example, a circuit component may be formed on a glasssubstrate to “isolate” the component in order to reduce effects of noisefrom other components of the mobile device.

Radio-frequency (RF) filters may include integrated passive devices(IPD), such as a passive-on-glass (POG) device (e.g., a capacitor and/oran inductor). Glass may be desirable for its low loss tangent and is apreferred substrate material for example when used for RF IPD, acousticresonators/filters and RF MEMS switches. Wideband filters are criticalfor new radio designs, e.g., 5G RF frontend circuits, to offer higherspeed communication. Among the available RF filter technologies,integrated passive devices (including metal insulator metal (MIM)capacitors and inductors) can achieve high quality (HQ) for both L and Cdevices. Other RF filter technologies include acoustic filters, such assurface acoustic wave (SAW) filter, bulk acoustic wave (BAW) filter,film bulk acoustic resonator (FBAR)). HQ IPD are desirable for highperformance RF Frontend (RFFE) applications to not only for matchingcomponents but also for LC filters, that require low insertion loss inwideband applications (e.g., for 5G wideband filter application). POGand its application to RF wideband filters has been demonstrated in theart. However, there is a need for improved filter performance along withreducing the filter size.

Accordingly, there is a need for systems, apparatus, and methods thatimprove on the conventional approaches including the methods, system andapparatus provided herein.

SUMMARY

The following presents a simplified summary relating to one or moreaspects and/or examples associated with the apparatus and methodsdisclosed herein. As such, the following summary should not beconsidered an extensive overview relating to all contemplated aspectsand/or examples, nor should the following summary be regarded toidentify key or critical elements relating to all contemplated aspectsand/or examples or to delineate the scope associated with any particularaspect and/or example. Accordingly, the following summary has the solepurpose to present certain concepts relating to one or more aspectsand/or examples relating to the apparatus and methods disclosed hereinin a simplified form to precede the No errors found detailed descriptionpresented below.

At least one aspect includes a device including a passive portion havingat least one metal insulator metal (MIM) capacitor and at least one2-dimensional (2D) inductor. The device further includes a substrate andthe passive portion is formed on the substrate. A magnetic core isembedded in the substrate. A 3-dimensional (3D) inductor is alsoincluded having windings formed at least in part in the substrate and atleast a portion of the windings being formed around the magnetic core.

At least one additional aspect includes a method for manufacturing adevice. The method includes embedding a magnetic core a substrate. Apassive portion is formed on the substrate, wherein the passive portionhas at least one metal insulator metal (MIM) capacitor and at least one2-dimensional (2D) inductor. A 3-dimensional (3D) inductor is formedhaving windings formed at least in part in the substrate and at least aportion of the windings being formed around the magnetic core.

Other features and advantages associated with the apparatus and methodsdisclosed herein will be apparent to those skilled in the art based onthe accompanying drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of aspects of the disclosure and many ofthe attendant advantages thereof will be readily obtained as the samebecomes better understood by reference to the following detaileddescription when considered in connection with the accompanying drawingswhich are presented solely for illustration and not limitation of thedisclosure.

FIG. 1 illustrates a partial side view of a semiconductor device with aceramic substrate in accordance with some examples of the disclosure.

FIG. 2 illustrates a schematic diagram of a multiplexer in accordancewith some examples of the disclosure.

FIG. 3 illustrates a plan view and perspective view of a semiconductordevice in accordance with some examples of the disclosure.

FIG. 4 illustrates a schematic diagram of a radio frequency (RF) frontend (RFFE) module in accordance with some examples of the disclosure.

FIGS. 5A-F illustrate further example portions of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure.

FIGS. 6A-C illustrate further example portions of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure.

FIGS. 7A-K illustrate further example portions of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure.

FIG. 8 illustrates a flowchart of a method for manufacturing asemiconductor device in accordance with some examples of the disclosure.

FIG. 9 illustrates a mobile device in accordance with some examples ofthe disclosure.

FIG. 10 illustrates various electronic devices that may be integratedwith any of the aforementioned devices in accordance with variousexamples of the disclosure.

In accordance with common practice, the features depicted by thedrawings may not be drawn to scale. Accordingly, the dimensions of thedepicted features may be arbitrarily expanded or reduced for clarity. Inaccordance with common practice, some of the drawings are simplified forclarity. Thus, the drawings may not depict all components of aparticular apparatus or method. Further, like reference numerals denotelike features throughout the specification and figures.

DETAILED DESCRIPTION

Aspects of the present disclosure are illustrated in the followingdescription and related drawings directed to specific aspects. Alternateaspects may be devised without departing from the scope of the teachingsherein. Additionally, well-known elements of the illustrative aspectsherein may not be described in detail or may be omitted so as not toobscure the relevant details of the teachings in the present disclosure.

In certain described example implementations, instances are identifiedwhere various component structures and portions of operations can betaken from known, conventional techniques, and then arranged inaccordance with one or more aspects. In such instances, internal detailsof the known, conventional component structures and/or portions ofoperations may be omitted to help avoid potential obfuscation of theconcepts illustrated in the illustrative aspects disclosed herein.

The terminology used herein is for the purpose of describing particularaspects only and is not intended to be limiting As used herein, thesingular forms “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “comprises,” “comprising,”“includes,” and/or “including,” when used herein, specify the presenceof stated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Recently, a new series of thin alumina ceramic ribbon substrate has beenintroduced which not only has lower loss tangent (1e⁻⁴, one ordersmaller than glass of 1e⁻³), but also offers 30× higher thermalconductivity (˜36 W/Ko-m) better than glass substrate. Thus, the aluminaceramic material, with lower loss tangent and higher thermalconductivity along with higher coefficient of thermal expansion (CTE) vsglass. The alumina ceramic substrate can be used as an alternativesubstrate for RF IPD, acoustic resonators/filters and RF MEMS switches.Additionally, it may be used for silicon CMOS devices for layer transferto form RF silicon-on-insulator (SOI).

As noted above, there is a need for improved filter performance alongwith reduced filter size. The conventional POG has a thick glasssubstrate (e.g., 700 um), whereas the alumina ceramic substratediscussed herein is a thin substrate (e.g., ˜40-80 um), which aids inreducing the filter size. Additionally, the high thermal conductivityand low loss tangent of the alumina ceramic substrate is preferred forRF filter devices use high power handling (e.g., filters in the TXpath). Even though improved performance can be expected for the 2D IPDfilters on an alumina ceramic substrate under TX high power handling, asmaller compact filter device is desirable for mobile UE devices. Thiscan be obtained by forming a 3D solenoid inductor with through-substratevia and metal fill. However, for the traditional 3D inductor (e.g., 3Dsolenoid inductor), a high density inductor cannot be formed using thesubstrate itself, because the permeability is unity, which is the sameas for the 2D planar inductor. Thus, various aspects disclosed hereinovercome this limitation by forming a magnetic core which has a higherpermeability than the substrate for the 3D inductor.

FIG. 1 illustrates a partial side view of a passive device in accordancewith some examples of the disclosure. As shown in FIG. 1, asemiconductor device 100 can include a passive portion 105 formed on asubstrate 150 (such as an alumina ceramic substrate, which will be usedherein in some examples for illustration). The passive portion 105 maybe formed as a multilayer component including a first metal layer 110(M1 110) applied on the alumina substrate 150. As illustrated, thepassive portion 105 includes a plurality of metal layers, such as asecond metal layer 120 (M2 120), and a third metal layer 130 (M3 130),in addition to metal layer M1 110. It will be appreciated thatillustrated aspects are used solely to provide an example and not tolimit the various aspects disclosed. For example, the passive portionmay include more or less metal layers than illustrated. One or morethrough-substrate vias (e.g., via 115 and via 125), may bethrough-passivation vias, in one example, and are used to electricallycouple the metal layers. For example, M1 110 can be coupled to M2 120 byvias 115 and M2 120 can be coupled to M3 130 by vias 125 through thepassivation layers (e.g., 112 and 122). Additionally passive portion 105may also include a plurality of passivation/insulating layers, includinga first inter-layer dielectric (ILD) 112, a second ILD 122 and a thirdILD 132. A dielectric material of the first ILD 112, the second ILD 122and/or third ILD 132 may include polyimide (PI), benzocyclobuten (BCB),polybenzoxazole (PBO), an acrylic, an epoxy, and/or other materials, asillustrative, non-limiting examples. In some implementations, the firstILD 112, the second ILD 122 and or third ILD 132 may be differentmaterials. In other implementations, the first ILD 112, the second ILD122 and/or the third ILD 132 may be the same material. As discussedabove, one or more through-substrate vias, may be through-passivationvias (e.g., through-ILD), in one example, and used to electricallycouple between the metal layers, as discussed above.

A MIM capacitor 160 may be formed in the passive portion 105 andcomprises a portion of the first metal layer 110 (used as a bottom metallayer for the MIM capacitor 160), an insulating layer 114 and top metallayer 116 (TM 116) coupled to the second metal layer 120 by vias 115. Itwill be appreciated that in some aspects to form on or more MIMcapacitors 160 with good dielectric properties, like high capacitancedensity, low leakage current and high breakdown voltage, the dielectricinsulator may be deposited or anodized separately from the interlayerdielectrics (e.g., silicon oxide (SiOx), silicon nitride (SiNx) byplasma-enhanced chemical vapor deposition (PECVD) and tantalum pentoxide(Ta₂O₅) by anadization of Ta metal). In some aspects, the insulatinglayer 114 may be a silicon nitride (SiN) compound, silicon oxide (SiO₂)compound, aluminum oxide (Al₂O₃), tantalum pentoxide (Ta₂O₅), zirconiumdioxide (ZrO₂) or any other suitable insulating/dielectric material. Insome aspects, interconnection between the various layers using vias(e.g., vias 115 and/or vias 125) and one or more metal layers (e.g., M1110, M2 120 and/or M3 130) may be used to couple to the MIM capacitor160, 2D inductor 170, 3D inductor 180 and/or external devices. Forexample, an external device can be coupled to the various components(e.g., MIM capacitor 160, 2D inductor 170, 3D inductor 180, etc.) usingone or more external connectors (e.g., ball 190) through under bumpmetallization (UBM) 192 coupled to M3 130, via 125, M2 120, via 115and/or M1 110. The external connectors (e.g., wafer-level package (WLP)ball, solder balls, solder bumps, copper pillar bumps, or other externalconnectors) are illustrated as a ball 190. Additionally, the variousmetal layers and vias may be used to connect the MIM capacitor 160, 2Dinductor 170 and/or 3D inductor 180 to each other and/or internalcomponents of passive portion 105, such as other capacitors, inductors,etc. (not illustrated). It will be appreciated, that the two thick metallayers, M2 120 and M3 130, which in some examples may be on the order of8 um to 16 um in thickness, may be used to form the 2D inductor 170. The2D inductor 170 may be formed with its windings routed in one or more ofthe thick layers (M2 120 and/or M3 130) in a spiral configuration forimproved inductor quality factor (Q factor) and RF performance. The MIMcapacitor 160 may be formed in the passive portion 105. A 2D inductor170 may also be formed using the metal layers M1 110 and M2 120 As notedabove, the formation of MIM capacitors 160, 2D inductors 170 and othercomponents in an in the passive portion 105 are known and therefore willnot be further detailed herein.

The 3D inductor 180 may be formed using multiple winding portions. Forexample, a first portion of the windings 181 of the 3D inductor 180 maybe formed in substrate 150 using through-substrate vias 155 (e.g.,illustrated as a through alumina via (TAV) 155 in the alumina substrate150). A second portion of the windings 182 of the 3D inductor 180 may beformed by connections in at least one metal layer (e.g., as illustratedin M1 110 and M2 120) in the passive portion 105. The second portion ofthe windings 182 may also be formed using additional metal layers suchas M3 130 or other metal layers if available. The second portion of thewindings 182 of the 3D inductor 180 may be cross coupled to vias 155 toform an angled pattern (such as illustrated in the top graphic) or maybe coupled in a straight fashion to form concentric windings. A thirdportion of the windings 183 of the 3D inductor 180 may be formed byconnections in at least one metal layer (e.g., bottom metal layer 140(MA 140)) on a side of the substrate 150 opposite the passive portion105. The metal layers (M1 110, M2 120, M3 130, MA 140, TM 116) may beformed from high conductivity materials such as copper (Cu), aluminum(Al), gold (Au), alloys or combinations thereof.

As illustrated, the bottom metal layer 140, may be formed on the aluminasubstrate 150 and enclosed in bottom insulating/passivation layer, suchas bottom ILD 142. In addition to the bottom winding metal for the 3Dinductor, MA 140 can also serve as an interconnect for the components(e.g., MIM capacitor 160, 2D inductor 170, etc.) that can benefit fromhaving an interconnect from the bottom side of the substrate 150. Thethird portion of the windings 183, of the 3D inductor 180, may be formedby portions of MA 140. The third portion of the windings 183 may becross coupled to vias 155 to form an angled pattern or may be coupled ina straight fashion to form concentric windings. Additionally, one of thesecond portion of the windings 182 or the third portion of the windings183 may be angled and the other may be straight to form another windingconfiguration. It will be appreciated that the windings configurationsfor the 3D inductor 180 are not limited to any specific layout orconfiguration. For example, the MIM capacitor 160 can be formed from oneor more metal layers of the multiple metal layers in the passive portion105. As illustrated, at least a portion of the windings (e.g., 182) ofthe 3D inductor 180 is formed on at least one common metal layer (e.g.,M1 110) with the MIM capacitor 160. Additionally or alternatively, the2D inductor 170 may be formed on adjacent metal layers (M2 120 and M3130) of the multiple metal layers (e.g., M1, M2, M3, etc.) of thepassive portion 105. At least a portion of the windings (e.g., 182) ofthe 3D inductor 180 is formed on at least one common metal layer withthe 2D inductor (e.g., M2 120). However, other configurations may nothave any shared metal layers with the MIM capacitor 160 and/or 2Dinductor 170 or the common metal layers may be used for connecting toanother metal layer using vias, etc. Accordingly, it will be appreciatedthat the 3D inductors may be formed by through-substrate vias 155 (e.g.,through-alumina via (TAV)) and various front-side and back-sideprocesses. It will be appreciated that the illustrations anddescriptions provided herein are solely to provide examples and are notintended to limit the various aspects disclosed herein.

Regardless of the winding configurations of the 3D inductor 180, theembedded magnetic core 185 can be used to provide a high-quality andhigh-density 3D inductor 180. In some example configurations, themagnetic core extends beyond the windings of the 3D inductor. Themagnetic core may be formed from high magnetic permeability (high μ)metals such as at least one of iron (Fe), cobalt (Co) or nickel (Ni)and/or other ferrite materials. The magnetic core 185 may be embedded inthe substrate 150 using a core filler 152 to secure the magnetic core.The core filler 152 may be glass or ceramic, such as a glass or ceramicfrit or paste. The windings of the 3D inductor 180 are at leastpartially disposed around the magnetic core 185. In some configurationsthe windings of the 3D inductor 180 are entirely disposed around themagnetic core 185, which extends beyond the windings of the 3D inductor180, as illustrated. However, in alternative examples at least a portionof the windings of the 3D inductor may extend beyond the magnetic core185 and/or the magnetic core 185 may be contained within the windings ofthe 3D inductor so no portion of the magnet core 185 extends beyond the3D inductor 180. Accordingly, it will be appreciated that the variousillustrations and descriptions provided herein are solely to provideexamples and are not intended to limit the various aspects disclosedherein.

FIG. 2 illustrates a schematic diagram of a multiplexer in accordancewith some examples of the disclosure. In FIG. 2, the multiplexer 200 isillustrated as a diplexer 200, but it will be appreciated that thevarious aspects herein can be applied to many filter configurationsincluding a bandpass filter, diplexer, triplexer, etc. The diplexer 200includes a high band (HB) port 202, a low band (LB) port 204, and anantenna 206. A high band path 220 of the diplexer 200 includes a firstcapacitor 222 coupled to the HB port 202. A second capacitor 224 iscoupled in series with the first capacitor 222. A first inductor 226(B17) is coupled between capacitors 222 and 224. The first inductor 226has a third capacitor 228 coupled to ground and in series with the firstinductor 226. The first series coupled capacitor 224 is also coupled tothe antenna 206. A low band path 240 of the diplexer 200 includes asecond inductor 242 couple in series to the LB port 204 and in serieswith a third inductor 244. The low band path 240 also includes a fourthcapacitor 246 coupled between the second inductor 242 and third inductor244. The fourth capacitor 246 is also coupled to ground through a fourthinductor 248 (B4) which is in series with the fourth capacitor 246. Thesecond inductor 242 is also coupled to antenna 206. In operation, as isknown, the diplexer 200 will pass high frequency signals between the HBport 202 and the antenna 206. Likewise, the diplexer 200 will pass lowfrequency signals between the LB port 204 and the antenna 206. It willbe appreciated, the schematic diagram illustrated (e.g., number,connections and/or positions of passive elements) may be modified as iscommon for various filter designs and manufacturing considerations. Itwill be appreciated the passive components (e.g., MIM capacitor 160, 2Dinductor 170 and 2D inductor 180) may be used to form diplexer 200 or atleast a portion of diplexer 200. Further, it will be appreciated thatthe schematic diagram of diplexer 200 is merely an example provided forexplanation of the various aspects and is not intended to limit theaspects disclosed herein.

FIG. 3 illustrates a plan view and perspective view of a semiconductordevice 300 in accordance with some examples of the disclosure. As shownin FIG. 3, the semiconductor device 300 includes several 3D inductors310 and MIM capacitors 320 that could be used to for various devices,such as diplexer 200 illustrated in relation to FIG. 2. The MIMcapacitors 320 may be formed on an alumina ceramic substrate 350 orother high performance substrate as discussed herein. It will beappreciated from the foregoing that the semiconductor device 300 maycontain any of a number of components (e.g., MIM capacitors, 2Dinductors, 3D inductors, etc.) that can benefit the various aspectsdisclosed herein. The semiconductor device 300 also includes externalconnectors 352, which may be realized in any form known in the art(e.g., solder ball, copper pillar, etc.) to couple the semiconductordevice 300 to external circuits or devices. In the perspective view ofthe semiconductor device 300, the through-substrate vias, e.g.,through-alumina vias (TAV) 355 (similar to vias 155 in FIG. 1) may beused to form a portion of the winding for each 3D inductor 310. Asdiscussed in the foregoing, 3D inductors 310 may be formed usingmultiple winding portions (e.g., 311, 312 and 313). For example, a firstportion of the windings 311 of the 3D inductor 310 may be formed insubstrate 350 using through-substrate vias 355 (e.g., illustrated as aTAV 355 in the alumina substrate 350). A second portion of the windings312 of the 3D inductor 310 may be formed by connections in at least onemetal layer in the passive portion of that contains MIM capacitors 320.The second portion of the windings 312 of the 3D inductor 310 may becross coupled to vias 355 to form an angled pattern (such asillustrated). A third portion of the windings 313 of the 3D inductor 310may be formed by connections in at least one metal layer of on a side ofthe substrate 350 opposite the passive portion with the MIM capacitors320. As illustrated, the third portion of the windings 313 of the 3Dinductor 310 may be cross coupled to vias 355 in a generally straightfashion. However, it will be appreciated that the windingsconfigurations for the 3D inductors 310 are not limited to a specificlayout or configuration. Likewise, other capacitors, inductors or othercircuit elements may be included in the semiconductor device 300 as willbe appreciated by those skilled in the art. Accordingly, the foregoingillustrations and descriptions provided herein are solely to provideexamples and are not intended to limit the various aspects disclosedherein. Further, some of the elements discussed in relation to thevarious aspects disclosed herein are not illustrated (e.g., 2D inductor,magnetic core, various metal and ILD layers, etc.) in the plan andperspective views of FIG. 3 to aid in reducing complication of theimages.

FIG. 4 illustrates a schematic diagram of a RF front end (RFFE) module400 in accordance with some examples of the disclosure. As shown in FIG.4, RFFE module 400 may include a diplexer 200 according to aspects ofthe disclosure. The RFFE 400 includes power amplifiers 402,duplexer/filters 404, and a radio frequency (RF) switch module 406. Thepower amplifiers 402 amplify signal(s) to a certain power level fortransmission. The duplexer/filter 404 filters the input/output signalsaccording to a variety of different parameters, including frequency,insertion loss, rejection or other like parameters. In addition, the RFswitch module 406 may select certain portions of the input signals topass on to the rest of the RF front end module 400.

The RF front end module 400 also includes tuner circuitry 412 (e.g.,first tuner circuitry 412A and second tuner circuitry 412B), thediplexer 200, a capacitor 416, an inductor 418, a ground terminal 415and an antenna 414. The tuner circuitry 412 (e.g., the first tunercircuitry 412A and the second tuner circuitry 412B) includes componentssuch as a tuner, a portable data entry terminal (PDET), and a housekeeping analog to digital converter (UKADC). The tuner circuitry 412 mayperform impedance tuning (e.g., a voltage standing wave ratio (VSWR)optimization) for the antenna 414. The RF front end module 400 alsoincludes a passive combiner 408 coupled to a wireless transceiver (WTR)420. The passive combiner 408 combines the detected power from the firsttuner circuitry 412A and the second tuner circuitry 412B. The wirelesstransceiver 420 processes the information from the passive combiner 108and provides this information to a modem 430 (e.g., a mobile stationmodem (MSM)). The modem 430 provides a digital signal to an applicationprocessor (AP) 440.

As shown in FIG. 4, the diplexer 200 is between the tuner component ofthe tuner circuitry 412 and the capacitor 416, the inductor 418, and theantenna 414. The diplexer 200 may be placed between the antenna 414 andthe tuner circuitry 412 to provide high system performance from the RFfront end module 400 to a chipset including the wireless transceiver420, the modem 430 and the application processor 440. The diplexer 200also performs frequency domain multiplexing on both high bandfrequencies and low band frequencies. After the diplexer 200 performsits frequency multiplexing functions on the input signals, the output ofthe diplexer 200 is fed to an optional LC (inductor/capacitor) networkincluding the capacitor 416 and the inductor 418. The LC network whichmay provide extra impedance matching components for the antenna 414,when desired. Then a signal with the particular frequency is transmittedor received by the antenna 414. It will be appreciated that the variouscomponents illustrated may be separated multiple components orintegrated into less components. Further, the various elements need notbe included in RFFE modules according to various aspects disclosedherein, as determined by conventional design considerations and allvariations are not attempted to be illustrated. Accordingly, theillustrations and descriptions provided herein are solely to provideexamples and are not intended to limit the various aspects disclosedherein.

FIG. 5A illustrates a portion of a fabrication process of asemiconductor device in accordance with some examples of the disclosure.As shown in FIG. 5A, there are some basic processes related to thesubstrate fabrication. At 502, a substrate (e.g., 150, 350) is providedand vias (e.g., TAV 155, 355) are formed in the substrate. The substratemay be an alumina ceramic substrate including a polished smoothing film(discussed below). The through-substrate vias (e.g., formed through thealumina substrate and may also be referred herein as through alumina viaor TAV. The TAV may be formed by laser drilling (e.g., laser ablation),plasma etching (dry etch) or photo induced etching (wet etch) or othermethods. The TAV may be filled with copper, gold or other suitableconductive materials. Filling the TAV with conductive material may beperformed by sputtering, plating or any other known technique. TAVsallow for the electrical coupling through the alumina and according toaspects disclosed herein are also used for forming a portion of thewindings of 3D inductors. In 504, a magnetic core is embedded in thesubstrate. For example, a cavity is formed in the substrate. The cavitycan be formed by an etching substrate to form the cavity or any othersuitable technique. The magnetic core can then be inserted in thesubstrate, a ceramic fill/paste can be used to secure the magnetic core.The substrate can be planarized/polished before and/or after theembedding of the magnetic core to provide that the substrate has aplanar surface.

As part of fabricating the substrate, it will be appreciated thatwithout adequate planarity, fabricating TAVs, etc. would not bepractical and for some substrates that have rough surfaces. Accordingly,additional fabrication processes may be performed. For example, thealumina ceramic substrate may have a smoothing film deposited. Thesmoothing film can be selected from amorphous thermally-conductiveelectrically insulative films, such as discussed herein. For example,the depositing may be performed by a room-temperature physical vapordeposition process (RT-PVD) for depositing an alumina nitride (AlN)film. Alternatively, depositing may be performed by low temperaturechemical vapor deposition (CVD) for depositing a diamond film or asilicon-carbide film. After the film is deposited, a polishing operationmay be performed on the smoothing film to form a planar substrate-filmsurface on the alumina substrate. The polishing can be performed by avariety of methods depending on the film material, fabricationpreferences, etc. For example, the smoothing film may be mechanicallypolished or may be polished by performing a chemical mechanical polish(CMP) process. The following figures provide some example processingtechniques, merely for illustration, and are not intended to limit thevarious aspects herein.

FIG. 5B illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 5B, the substrate 550 (illustrated anddiscussed hereafter as alumina ceramic substrate 550) has the smoothingfilm (not explicitly illustrated) which has been processed to form aplanar substrate surface 551. As discussed herein, the raw aluminaceramic substrate is processed to planarize the surface(s) (e.g.,smoothing film and CMP, as discussed herein). At this point in theprocess, the surface 551 is sufficiently planarized to allow for furtherprocessing, As illustrated, substrate via openings 510 are formedthrough the alumina substrate 550. The substrate via openings 510 may beformed by laser drilling (e.g., laser ablation), plasma etching (dryetch) or photo induced etching (wet etch) or other methods. It will beappreciated that the illustrated processes of FIG. 5B are providedsolely as an example illustration and is not intended to limit thevarious aspects disclosed herein.

FIG. 5C illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 5C, the alumina ceramic substrate 550 hasthe substrate via openings 510 (not illustrated) filled to formthrough-substrate vias 555, illustrated as TAVs 555. The TAVs 555 may befilled with copper, gold or other suitable conductive materials. Fillingthe TAV 555 with conductive material may be performed by sputtering,plating or any other known technique. TAVs allow for the electricalcoupling through the alumina and according to aspects disclosed hereinare also used for forming a portion of the windings of 3D inductors. Itwill be appreciated that the illustrated processes of FIG. 5C areprovided solely as an example illustration and is not intended to limitthe various aspects disclosed herein.

FIG. 5D illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 5D, the alumina ceramic substrate 550 hasthe TAVs 555 formed. The processing continues with the formation of acavity 560 in the alumina ceramic substrate 550. The cavity 560 can beformed by an etching the alumina ceramic substrate 550 to form thecavity 560 or any other suitable technique. It will be appreciated thatthe illustrated processes of FIG. 5D are provided solely as an exampleillustration and is not intended to limit the various aspects disclosedherein.

FIG. 5E illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 5E, the alumina ceramic substrate 550 hasthe TAVs 555 and cavity 560 formed. The processing continues with theembedding of a magnetic core 585 in the cavity 560 in the aluminaceramic substrate 550. The magnetic core may be formed from highmagnetic permeability (high μ) metals such as at least one of iron (Fe),cobalt (Co) or nickel (Ni) and/or other ferrite materials. It will beappreciated that the illustrated processes of FIG. 5E are providedsolely as an example illustration and is not intended to limit thevarious aspects disclosed herein.

FIG. 5F illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 5F, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded within. The processingcontinues with a core filler 552 used to secure the magnetic core 585embedded in the alumina ceramic substrate 550. The core filler 552 maybe glass or ceramic frit or paste. It will be appreciated that theillustrated processes of FIG. 5F are provided solely as an exampleillustration and is not intended to limit the various aspects disclosedherein.

FIG. 6A illustrates a further example portion of a fabrication process600 of a semiconductor device in accordance with some examples of thedisclosure. In block 602, the backside target alignment is performed toensure the alignment of the TAV and the bottom layer (e.g., copper (Cu)layer, masks, etc.). In block 604, the fabrication process furtherincludes forming backside interconnect metal (see, e.g., metal layer 140(MA) in FIG. 1). The following figures provide some example processingtechniques, merely for illustration, and are not intended to limit thevarious aspects herein.

FIG. 6B illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure, which continues from FIG. 5F. As shown in FIG. 6B, thealumina ceramic substrate 550 has the TAVs 555 and the magnetic core 585embedded and secured by core filler 552. The processing continues with abackside target alignment to a target 610 being performed to ensure thealignment of the TAVs 555 and subsequent processing to form a bottommetal layer (e.g., depositing, patterning, etching, etc.). It will beappreciated that the illustrated processes of FIG. 6B are providedsolely as an example illustration and is not intended to limit thevarious aspects disclosed herein.

FIG. 6C illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 6C, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The processing continues with forming the bottom metal layer640 (MA), may be formed on the alumina substrate 550 and enclosed in abottom ILD 642 (ILD-A). As illustrated bottom the metal layer 640 can bedeposited on the bottom surface of alumina ceramic substrate 550.Optionally, not expressly illustrated, a seed layer may be formed on thebottom surface of alumina ceramic substrate 550 to aid in the adhesionand formation of the bottom metal layer 640. The bottom metal layer 640can be patterned and etched after being deposited on bottom the metallayer 640, to support the formation of various passive devices, activedevices and/or interconnections. It will be appreciated that theillustrated processes of FIG. 6C are provided solely as an exampleillustration and is not intended to limit the various aspects disclosedherein.

FIG. 7A illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. The fabrication process 750 continues at 702 with formingtopside target alignment to TAV-Cu to ensure proper alignment for thebottom electrode/M1 patterned elements. In 703, the bottom electrode(e.g., M1 110 in FIG. 1) can be formed for the MIM capacitors (e.g.,160, 320), inductors (e.g., 170, 180), etc. A PECVD process can be usedto form the dielectrics of the MIM capacitors or an anodic oxide can beformed for the MIM capacitor. The fabrication process 750 continues at704 with forming the top metal (e.g., TM 116) of the MIM capacitor. At705, a first ILD (ILD-1) can be deposited on M1 using a spin coat andthermal cure of the ILD-1 polymer (e.g., PI or BCB). Further, in 705,the ILD-1 is opened (e.g., photomask and etched) to form a first set ofvias (V1) for coupling a second metal layer (M2) to M1 and to TM of theMIM capacitor. The fabrication process 750 continues at 706 with formingthe second metal layer (see, e.g., M2 120). The second metal layer M2can be used for the MIM capacitor(s), 2D inductor(s) (e.g., 170) and/or3D inductor(s) (e.g., 180, 310). The M2 layer may be a thick metallayer, as discussed herein. At 707, a second ILD (ILD-2) can bedeposited on M2 via a spin coat and thermal cure of the ILD-2 polymer(e.g., PI or BCB). Further, at 707, the ILD-2 is opened to form vias(V2) for coupling a third metal layer (M3) to M2. The fabricationprocess 750 continues at 708 with forming the third metal layer (M3).The third metal layer M3 can be used for the 2D inductors and otherconnections and/or components. The third metal layer M3 layer in someaspects may also be a thick metal layer, as discussed herein. At 709, athird ILD (ILD-3) can be deposited on M3 via a spin coat and thermalcure of the ILD-3 polymer (e.g., PI or BCB). Further, at 709, the ILD-3is opened to form vias for coupling the third metal layer (M3) toexternal connectors (e.g., ball, Cu pillar, CU bump, etc.) The externalconnectors (e.g., WLP ball 190, in FIG. 1) can be formed as a finalportion of the fabrication process. It will be appreciated from theforegoing that many of the fabrication processes are conventionalprocesses known in the art. Accordingly, it will be appreciated from theforegoing disclosure that additional and/or alternate processes forfabricating the various aspects disclosed herein will be apparent tothose skilled in the art and a literal rendition of all the potentialvariations in the processes discussed above will not be provided orillustrated in the included drawings. However, to aid in the disclosureof the various aspects disclosed, the following figures provide someexample processing techniques, merely for illustration, and are notintended to limit the various aspects herein.

FIG. 7B illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure, which follows from FIG. 6C. As shown in FIG. 7B, the aluminaceramic substrate 550 has the TAVs 555 and the magnetic core 585embedded and secured by core filler 552. The bottom metal layer 640 (MA)is formed on the alumina substrate 550 and enclosed in bottom ILD 642.As illustrated, the processing continues with a topside target alignmentto a target 701 being performed to ensure the alignment of the TAVs 555and subsequent masks for forming the various top metal layers. It willbe appreciated that the illustrated processes of FIG. 7B are providedsolely as an example illustration and is not intended to limit thevarious aspects disclosed herein.

FIG. 7C illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7C, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on the aluminasubstrate 550 and enclosed in bottom ILD 642. As illustrated, theprocessing continues with a first metal layer 710 (M1) being depositedon the top surface 555 of the alumina ceramic substrate 550. Asmentioned above, and not expressly illustrated, a seed layer may beformed on the surface 555 to aid in the adhesion and formation of thefirst metal layer 710. The first metal layer 710 can be patterned andetched after being deposited on the surface 555, to support theformation of various passive devices, active devices and/orinterconnections. It will be appreciated that the illustrated processesof FIG. 7C are provided solely as an example illustration and is notintended to limit the various aspects disclosed herein.

FIG. 7D illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7D, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) is formed on a top surface of the aluminasubstrate 550. As illustrated, the processing continues with adielectric film 714 being deposited over the first metal layer 710 (M1)and also the alumina ceramic substrate 550 and core filler 552. Thedielectric film 714 can be used in the formation of one or more MIMcapacitors and/or other devices. In some aspects, the dielectric film714 may only cover a portion of the first metal layer, such as in aportion where the MIM capacitor will be formed. It will be appreciatedthat the illustrated processes of FIG. 7C are provided solely as anexample illustration and is not intended to limit the various aspectsdisclosed herein.

FIG. 7D illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7D, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) is formed on a top surface of the aluminasubstrate 550. As illustrated, the processing continues with adielectric film 714 being deposited over the first metal layer 710 (M1)and also the alumina ceramic substrate 550 and core filler 552. Thedielectric film 714 can be used to support the formation of one or moreMIM capacitors and/or other devices. It will be appreciated that theillustrated processes of FIG. 7D are provided solely as an exampleillustration and is not intended to limit the various aspects disclosedherein.

FIG. 7E illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7E, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been deposited, patterned and etched anddielectric film 714 applied. As illustrated, the processing continueswith a top metal layer 716 being formed over a portion of the dielectricfilm 610 as part of the formation of a MIM capacitor. It will beappreciated that in alternative configurations, the top metal layer maynot be used and the M2 layer may be used as the top electrode of a MIMcapacitor. Accordingly, it will be appreciated that the illustratedprocesses of FIG. 7E are provided solely as an example illustration andis not intended to limit the various aspects disclosed herein.

FIG. 7F illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7F, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion. To avoidrecitation of all these aspects, the various elements formed to thispoint will be referred to as “the assembly”. As illustrated, theprocessing continues with a first inter-layer dielectric (ILD) 712 beingdeposited over the assembly. The first ILD 712 may be formed ofpolyimide (PI), benzocyclobuten (BCB), polybenzoxazole (PBO), anacrylic, an epoxy, and/or other materials, as illustrative non-limitingexamples. The first ILD 712 is patterned and etched to form openings 711in the first ILD 712 to allow for connections to the various metallayers (e.g., M1 and 716) of the assembly covered by the first ILD 712.Additionally, the formation of the openings 711 also includes formingopenings in the dielectric film 714 in some portions to allow access tothe first metal layer 710. It will be appreciated that the illustratedconfiguration of FIG. 7F is provided solely as an example illustrationand is not intended to limit the various aspects disclosed herein.

FIG. 7G illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7G, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion, with the assemblycovered by first ILD 712. As illustrated, the processing continues withvias 715 being formed in the first ILD 712 to allow for connections tothe various metal layers (e.g., M1 and 716) and the newly formed secondmetal layer 720 (M2). It will be appreciated that the vias 715 wereformed in the openings 711 (not illustrated) and may be formed in aseparate process or as part of the formation of the second metal layer720 (M2). The second metal layer 720 can be patterned and etched, afterbeing deposited on the first ILD 712, to support the formation ofvarious passive devices, active devices and/or interconnections, asdiscussed herein. It will be appreciated that the illustratedconfiguration of FIG. 7G is provided solely as an example illustrationand is not intended to limit the various aspects disclosed herein.

FIG. 7H illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7H, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion, with the assemblycovered by first ILD 712 and the second metal layer 720 has been formed.As illustrated, the processing continues with a second ILD 722 beingdeposited over the first ILD 712 and second metal layer 720. The secondILD 722 may be formed of polyimide (PI), benzocyclobuten (BCB),polybenzoxazole (PBO), an acrylic, an epoxy, and/or other materials, asillustrative non-limiting examples. The second ILD 722 is also patternedand etched to form one or more openings 724, to allow access to one ormore portions of the second metal layer 720. It will be appreciated thatthe illustrated configuration of FIG. 7H is provided solely as anexample illustration and is not intended to limit the various aspectsdisclosed herein.

FIG. 7I illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7I, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion, with the assemblycovered by first ILD 712, the second metal layer 720 has been formed andsecond ILD 722 applied. As illustrated, the processing continues withvias 725 being formed in the second ILD 722 to allow for connections tothe various portions of the second metal layer 720 and the newly formedthird metal layer 730 (M3). It will be appreciated that the vias 725were formed in the openings 724 (not illustrated) and may be formed in aseparate process or as part of the formation of the third metal layer730 (M3). The third metal layer 730 can be patterned and etched, afterbeing deposited on the second ILD 722, to support the formation ofvarious passive devices, active devices and/or interconnections, asdiscussed herein. It will be appreciated that the illustratedconfiguration of FIG. 7I is provided solely as an example illustrationand is not intended to limit the various aspects disclosed herein.

FIG. 7J illustrates a further example portion of a fabrication processof a semiconductor device in accordance with some examples of thedisclosure. As shown in FIG. 7J, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion, with the assemblycovered by first ILD 712. The second metal layer 720 has been formed,second ILD 722 applied and third metal layer 730 formed. As illustrated,the processing continues with a third ILD 732 being deposited over thesecond ILD 722 and third metal layer 730. The third ILD 732 may beformed of polyimide (PI), benzocyclobuten (BCB), polybenzoxazole (PBO),an acrylic, an epoxy, and/or other materials, as illustrativenon-limiting examples. The third ILD 732 is also patterned and etched toform one or more openings 734, to allow access to one or more portionsof the third metal layer 730. It will be appreciated that theillustrated configuration of FIG. 7J is provided solely as an exampleillustration and is not intended to limit the various aspects disclosedherein.

FIG. 7K illustrates a further example portion of a fabrication processof a semiconductor device 700 in accordance with some examples of thedisclosure. As shown in FIG. 7K, the alumina ceramic substrate 550 hasthe TAVs 555 and the magnetic core 585 embedded and secured by corefiller 552. The bottom metal layer 640 (MA) is formed on a bottomsurface of the alumina substrate 550 and enclosed in bottom ILD 642. Thefirst metal layer 710 (M1) has been formed and dielectric film 714applied, with the top metal layer 716 over a portion, with the assemblycovered by first ILD 712. The second metal layer 720 has been formed,second ILD 722 applied and third metal layer 730 is formed with thethird ILD 732 applied. As illustrated, the processing continues with thethird ILD 732 having one or more vias for coupling the third metal layer730 (M3) to external connections. The via, as illustrated, may be formedas an under bump metal layer (UBM) 792 on which an external connector(e.g., probe; WLP ball, Cu pillar, CU bump, etc.) is formed. In theillustrated example, a WLP ball 790, can be formed as a final portion ofthe fabrication process. In the final configuration, the variouscomponents, such as MIM capacitor 760, 2D inductor 770 and 3D inductormay be formed from the various metal layers, vias, etc., as discussedherein. It will be appreciated that the illustrated configuration ofFIG. 7K is provided solely as an example illustration and is notintended to limit the various aspects disclosed herein.

The various devices, processes and functionalities disclosed herein maybe designed and configured into computer files (e.g., RTL, GDSII,GERBER, etc.) stored on computer-readable media. Some or all such filesmay be provided to fabrication handlers who fabricate devices based onsuch files. Resulting products may include semiconductor wafers that arethen cut into semiconductor die and packaged into a semiconductor chip.The chips may then be employed in devices described above.

In order to fully illustrate aspects of the present disclosure, methodsof fabrication are presented. Other methods of fabrication are possible,and discussed fabrication methods are presented only to aidunderstanding of the concepts disclosed herein.

It will be appreciated from the foregoing that there are various methodsfor fabricating semiconductors including a 3D inductor with a magneticcore embedded in a substrate as disclosed herein. FIG. 8 illustrates aflowchart of a method for manufacturing a semiconductor device inaccordance with some examples of the disclosure. As shown in FIG. 8, thepartial method 800 may begin in block 802 with embedding a magnetic corein a substrate. The partial method 800 may continue in block 804 withforming a passive portion on the substrate, wherein the passive portionhas at least one metal insulator metal (MIM) capacitor and at least one2-dimensional (2D) inductor. The partial method 800 may continue inblock 806 with forming a 3-dimensional (3D) inductor having windingsformed at least in part in the substrate and at least a portion of thewindings being formed around the magnetic core. Optional aspects canalso be recognized from the foregoing disclosure. For example,optionally the method 800 in relation to embedding the magnetic core cancontinue, at block 808, with forming a cavity for the embedded magneticcore in the substrate. At block 810, the method 800 continues withinserting the magnetic core in the cavity. At block 812, the method 800continues with securing the magnetic core in the cavity using fillermaterial. At block 814, the method 800 continues with polishing theembedded the magnetic core to form a planar surface with a surface ofthe substrate. These and additional aspects are discussed in theforegoing disclosure. Accordingly, it will be appreciated from theforegoing disclosure that additional processes for fabricating thevarious aspects disclosed herein will be apparent to those skilled inthe art and a literal rendition of the processes discussed above willnot be provided or illustrated in the included drawings.

FIG. 9 illustrates a mobile device in accordance with some examples ofthe disclosure. Referring now to FIG. 9, a block diagram of a mobiledevice that is configured according to example aspects is depicted andgenerally designated mobile device 900. In some aspects, mobile device900 may be configured as a wireless communication device. As shown,mobile device 900 includes processor 901. Processor 901 may becommunicatively coupled to memory 932 over a link, which may be adie-to-die or chip-to-chip link. Mobile device 900 also includes display928 and display controller 926, with display controller 926 coupled toprocessor 901 and to display 928.

In some aspects, FIG. 9 may include coder/decoder (CODEC) 934 (e.g., anaudio and/or voice CODEC) coupled to processor 901; speaker 936 andmicrophone 938 coupled to CODEC 934; and wireless circuitry 940 (whichmay include a modem, RF circuitry, filters, etc., which may beimplemented using one or more semiconductor devices with aluminasubstrates, 3D inductors and embedded magnetic cores, as disclosedherein) coupled to wireless antenna 942 and to processor 901.

In a particular aspect, where one or more of the above-mentioned blocksare present, processor 901, display controller 926, memory 932, CODEC934, and wireless controller 940 can be included in a system-in-packageor system-on-chip device 922. Input device 930 (e.g., physical orvirtual keyboard), power supply 944 (e.g., battery), display 928, inputdevice 930, speaker 936, microphone 938, wireless antenna 942, and powersupply 944 may be external to system-on-chip device 922 and may becoupled to a component of system-on-chip device 922, such as aninterface or a controller.

It should be noted that although FIG. 9 depicts a mobile device,processor 901 and memory 932 may also be integrated into a set top box,a music player, a video player, an entertainment unit, a navigationdevice, a personal digital assistant (PDA), a fixed location data unit,a computer, a laptop, a tablet, a communications device, a mobile phone,an Internet of things (IoT) device or other similar devices.

FIG. 10 illustrates various electronic devices that may be integratedwith any of the aforementioned integrated device or semiconductor deviceaccordance with various examples of the disclosure. For example, amobile phone device 1002, a laptop computer device 1004, and a fixedlocation terminal device 1006 may each be consider generally userequipment (UE) and may include a semiconductor device 1000 as describedherein. The semiconductor device 1000 may be, for example, any of theintegrated circuits, dies, integrated devices, integrated devicepackages, integrated circuit devices, device packages, integratedcircuit (IC) packages, package-on-package devices described herein. Thedevices 1002, 1004, 1006 illustrated in FIG. 10 are merely an example.Other electronic devices may also feature the semiconductor device 1000including, but not limited to, a group of devices (e.g., electronicdevices) that includes mobile devices, hand-held personal communicationsystems (PCS) units, portable data units such as personal digitalassistants, global positioning system (GPS) enabled devices, navigationdevices, set top boxes, music players, video players, entertainmentunits, fixed location data units such as meter reading equipment,communications devices, smartphones, tablet computers, computers,wearable devices, servers, routers, electronic devices implemented invehicles (e.g., autonomous vehicles), an Internet of things (IoT) deviceor any other device that stores or retrieves data or computerinstructions or any combination thereof.

It will be appreciated that various aspects disclosed herein can bedescribed as functional equivalents to the structures, materials and/ordevices described and/or recognized by those skilled in the art. Forexample, in one aspect, an apparatus may comprise a means for performingthe various functionalities discussed above. It will be appreciated thatthe aforementioned aspects are merely provided as examples and thevarious aspects claimed are not limited to the specific referencesand/or illustrations cited as examples.

One or more of the components, processes, features, and/or functionsillustrated in FIGS. 1-10 may be rearranged and/or combined into asingle component, process, feature or function or incorporated inseveral components, processes, or functions. Additional elements,components, processes, and/or functions may also be added withoutdeparting from the disclosure. It should also be noted that FIGS. 1-10and corresponding description in the present disclosure are not limitedto dies and/or ICs. In some implementations, FIGS. 1-10 and itscorresponding description may be used to manufacture, create, provide,and/or produce integrated devices. In some implementations, a device mayinclude a die, an integrated device, a die package, an integratedcircuit (IC), a device package, an integrated circuit (IC) package, awafer, a semiconductor device, a package on package (PoP) device, and/oran interposer.

As used herein, the terms “user equipment” (or “UE”), “user device,”“user terminal,” “client device,” “communication device,” “wirelessdevice,” “wireless communications device,” “handheld device,” “mobiledevice,” “mobile terminal,” “mobile station,” “handset,” “accessterminal,” “subscriber device,” “subscriber terminal,” “subscriberstation,” “terminal,” and variants thereof may interchangeably refer toany suitable mobile or stationary device that can receive wirelesscommunication and/or navigation signals. These terms include, but arenot limited to, a music player, a video player, an entertainment unit, anavigation device, a communications device, a smartphone, a personaldigital assistant, a fixed location terminal, a tablet computer, acomputer, a wearable device, a laptop computer, a server, an automotivedevice in an automotive vehicle, and/or other types of portableelectronic devices typically carried by a person and/or havingcommunication capabilities (e.g., wireless, cellular, infrared,short-range radio, etc.). These terms are also intended to includedevices which communicate with another device that can receive wirelesscommunication and/or navigation signals such as by short-range wireless,infrared, wireline connection, or other connection, regardless ofwhether satellite signal reception, assistance data reception, and/orposition-related processing occurs at the device or at the other device.In addition, these terms are intended to include all devices, includingwireless and wireline communication devices, that are able tocommunicate with a core network via a radio access network (RAN), andthrough the core network the UEs can be connected with external networkssuch as the Internet and with other UEs. Of course, other mechanisms ofconnecting to the core network and/or the Internet are also possible forthe UEs, such as over a wired access network, a wireless local areanetwork (WLAN) (e.g., based on IEEE 802.11, etc.) and so on. UEs can beembodied by any of a number of types of devices including but notlimited to printed circuit (PC) cards, compact flash devices, externalor internal modems, wireless or wireline phones, smartphones, tablets,tracking devices, asset tags, and so on. A communication link throughwhich UEs can send signals to a RAN is called an uplink channel (e.g., areverse traffic channel, a reverse control channel, an access channel,etc.). A communication link through which the RAN can send signals toUEs is called a downlink or forward link channel (e.g., a pagingchannel, a control channel, a broadcast channel, a forward trafficchannel, etc.). As used herein the term traffic channel (TCH) can referto either an uplink/reverse or downlink/forward traffic channel.

The wireless communication between electronic devices can be based ondifferent technologies, such as code division multiple access (CDMA),W-CDMA, time division multiple access (TDMA), frequency divisionmultiple access (FDMA), Orthogonal Frequency Division Multiplexing(OFDM), Global System for Mobile Communications (GSM), 3GPP Long TermEvolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy(BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee/Thread) or otherprotocols that may be used in a wireless communications network or adata communications network. Bluetooth Low Energy (also known asBluetooth LE, BLE, and Bluetooth Smart) is a wireless personal areanetwork technology designed and marketed by the Bluetooth SpecialInterest Group intended to provide considerably reduced powerconsumption and cost while maintaining a similar communication range.BLE was merged into the main Bluetooth standard in 2010 with theadoption of the Bluetooth Core Specification Version 4.0 and updated inBluetooth 5.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any details described herein as “exemplary”is not to be construed as advantageous over other examples. Likewise,the term “examples” does not mean that all examples include thediscussed feature, advantage or mode of operation. Furthermore, aparticular feature and/or structure can be combined with one or moreother features and/or structures. Moreover, at least a portion of theapparatus described hereby can be configured to perform at least aportion of a method described hereby.

It should be noted that the terms “connected,” “coupled,” or any variantthereof, mean any connection or coupling, either direct or indirect,between elements, and can encompass a presence of an intermediateelement between two elements that are “connected” or “coupled” togethervia the intermediate element.

Any reference herein to an element using a designation such as “first,”“second,” and so forth does not limit the quantity and/or order of thoseelements. Rather, these designations are used as a convenient method ofdistinguishing between two or more elements and/or instances of anelement. Also, unless stated otherwise, a set of elements can compriseone or more elements.

Those skilled in the art will appreciate that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

Nothing stated or illustrated depicted in this application is intendedto dedicate any component, action, feature, benefit, advantage, orequivalent to the public, regardless of whether the component, action,feature, benefit, advantage, or the equivalent is recited in the claims.

Although some aspects have been described in connection with a device,it goes without saying that these aspects also constitute a descriptionof the corresponding method, and so a block or a component of a deviceshould also be understood as a corresponding method action or as afeature of a method action. Analogously thereto, aspects described inconnection with or as a method action also constitute a description of acorresponding block or detail or feature of a corresponding device. Someor all of the method actions can be performed by a hardware apparatus(or using a hardware apparatus), such as, for example, a microprocessor,a programmable computer or an electronic circuit. In some examples, someor a plurality of the most important method actions can be performed bysuch an apparatus.

In the detailed description above it can be seen that different featuresare grouped together in examples. This manner of disclosure should notbe understood as an intention that the claimed examples have morefeatures than are explicitly mentioned in each claim. Rather, thevarious aspects of the disclosure may include fewer than all features ofan individual example disclosed. Therefore, the following claims shouldhereby be deemed to be incorporated in the description, wherein eachclaim by itself can stand as a separate example. Although each claim byitself can stand as a separate example, it should be noted a dependentclaim can refer in the claims to a specific combination with one of theother claims. Further, other examples can also encompass or include acombination of one or more dependent claims with the subject matter ofany other dependent claim or a combination of any feature with otherdependent and independent claims. Such combinations are proposed herein,unless it is explicitly expressed or can be readily inferred that aspecific combination is not intended (e.g., contradictory aspects, suchas defining a feature as both an insulator and a conductor).Furthermore, it is also intended that features of a claim can beincluded in any other independent claim, even if said claim is notdirectly dependent on the independent claim.

In accordance with the various aspects disclosed herein, at least oneaspect includes a device (e.g., semiconductor device (e.g., 100, 200,300, 400, 700, etc., alone or integrated into another device) including:a passive portion (e.g., 105) having at least one metal insulator metal(MIM) capacitor (160, 320, 760) and at least one 2-dimensional (2D)inductor (170, 770). The device also includes a substrate (150, 350,550), where the passive portion (105) is formed on the substrate (150,350, 550). The device also includes a magnetic core (185, 585) embeddedin the substrate (150, 350, 550). The device also includes a3-dimensional (3D) inductor (180, 310, 780) having windings (181, 182,183, 311, 312, 313) formed at least in part in the substrate (150, 350,550) and at least a portion of the windings (181, 182, 183, 311, 312,313) being formed around the magnetic core (185, 585). It will beappreciated from the disclosure herein that the various technicaladvantages are provided by the various aspects disclosed. In at leastsome aspects, the 3D inductor having at least a portion of the windingsenclosing the embedded magnetic core allows for a better Q-Factor forthe inductor and better RF performance due to the increased permeabilityof the magnetic core in comparison to a conventional substrate. Further,the 3D inductor windings are in both the substrate and passive portion,which allows for a thinner structure of the semiconductor device thanconventional designs.

Other technical advantages will be recognized from various aspectsdisclosed herein and these technical advantages are merely provided asexamples and should not be construed to limit any of the various aspectsdisclosed herein.

It should furthermore be noted that methods, systems, and apparatusdisclosed in the description or in the claims can be implemented by adevice comprising means for performing the respective actions of thismethod.

Furthermore, in some examples, an individual action can be subdividedinto a plurality of sub-actions or contain a plurality of sub-actions.Such sub-actions can be contained in the disclosure of the individualaction and be part of the disclosure of the individual action.

While the foregoing disclosure shows illustrative examples of thedisclosure, it should be noted that various changes and modificationscould be made herein without departing from the scope of the disclosureas defined by the appended claims. The functions and/or actions of themethod claims in accordance with the examples of the disclosuredescribed herein need not be performed in any particular order.Additionally, well-known elements will not be described in detail or maybe omitted so as to not obscure the relevant details of the aspects andexamples disclosed herein. Furthermore, although elements of thedisclosure may be described or claimed in the singular, the plural iscontemplated unless limitation to the singular is explicitly stated.

What is claimed is:
 1. A device comprising: a passive portion having atleast one metal insulator metal (MIM) capacitor and at least one2-dimensional (2D) inductor; a substrate, wherein the passive portion isformed on the substrate; a magnetic core embedded in the substrate; anda 3-dimensional (3D) inductor having windings formed at least in part inthe substrate and at least a portion of the windings being formed aroundthe magnetic core, wherein the passive portion has multiple metallayers, the at least one 2D inductor is formed on adjacent metal layersof the multiple metal layers, and at least another portion of thewindings of the 3D inductor is formed on at least one common metal layerwith the at least one 2D inductor.
 2. The device of claim 1, wherein thesubstrate is an alumina ceramic substrate.
 3. The device of claim 1,wherein the substrate is formed of a material with a low loss tangent,high thermal conductivity and moderate coefficient of thermal expansion(CTE).
 4. The device of claim 1, wherein a first portion of the windingsof the 3D inductor are formed in substrate using through-substrate vias.5. The device of claim 4, wherein a second portion of the windings ofthe 3D inductor are formed by connections in at least one metal layer inthe passive portion.
 6. The device of claim 5, wherein a third portionof the windings of the 3D inductor are formed by connections in at leastone metal layer of on a side of the substrate opposite the passiveportion.
 7. The device of claim 1, wherein the magnetic core extendsbeyond the windings of the 3D inductor.
 8. The device of claim 1,wherein the at least one MIM capacitor is formed from adjacent metallayers of the multiple metal layers.
 9. The device of claim 8, whereinthe at least a portion of the windings of the 3D inductor is formed onat least one common metal layer with the MIM capacitor.
 10. The deviceof claim 1, further comprising: a cavity in the substrate, wherein themagnetic core is embedded in the cavity.
 11. The device of claim 1,wherein the device is incorporated into an apparatus selected from thegroup consisting of a music player, a video player, an entertainmentunit, a navigation device, a communications device, a mobile device, amobile phone, a smartphone, a personal digital assistant, a fixedlocation terminal, a tablet computer, a computer, a wearable device, anInternet of things (IoT) device, a laptop computer, a server, and adevice in an automotive vehicle.
 12. The device of claim 1, wherein theadjacent metal layers are thick metal layers.
 13. The device of claim 1,wherein the adjacent metal layers are on an order of 8 um to 16 um inthickness.
 14. The device of claim 1, wherein the device is a radiofrequency front end (RFFE).
 15. The device of claim 1, wherein themagnetic core is at least one of iron (Fe), cobalt (Co) or nickel (Ni).16. The device of claim 1, wherein the device is an integrated passivedevice.
 17. The device of claim 1, wherein the device is a multiplexer.18. The device of claim 1, wherein the device is a diplexer.
 19. Adevice comprising: a passive portion having at least one metal insulatormetal (MIM) capacitor and at least one 2-dimensional (2D) inductor; asubstrate, wherein the passive portion is formed on the substrate; amagnetic core embedded in the substrate; and a 3-dimensional (3D)inductor having windings formed at least in part in the substrate and atleast a portion of the windings being formed around the magnetic core,wherein the magnetic core extends beyond the windings of the 3Dinductor.
 20. A method for manufacturing a device, the methodcomprising: embedding a magnetic core in a substrate; forming a passiveportion on the substrate, wherein the passive portion has at least onemetal insulator metal (MIM) capacitor and at least one 2-dimensional(2D) inductor; and forming a 3-dimensional (3D) inductor having windingsformed at least in part in the substrate and at least a portion of thewindings being formed around the magnetic core, wherein embedding themagnetic core further comprises: forming a cavity for the embeddedmagnetic core in the substrate; inserting the magnetic core in thecavity; and securing the magnetic core in the cavity using fillermaterial.
 21. The method of claim 20, wherein the passive portion hasmultiple metal layers, the at least one 2D inductor is formed onadjacent metal layers of the multiple metal layers, and at least anotherportion of the windings of the 3D inductor is formed on at least onecommon metal layer with the at least one 2D inductor.
 22. The method ofclaim 20, wherein the substrate is an alumina ceramic substrate.
 23. Themethod of claim 20, wherein the substrate is formed of a material with alow loss tangent, high thermal conductivity and moderate coefficient ofthermal expansion (CTE).
 24. The method of claim 20, further comprising:forming through-substrate vias in the substrate, wherein the substrateis alumina ceramic substrate and the through-substrate vias are throughalumina vias.
 25. The method of claim 20, wherein a first portion of thewindings of the 3D inductor are formed in substrate usingthrough-substrate vias, and wherein a second portion of the windings ofthe 3D inductor are formed by connections in at least one metal layer inthe passive portion.
 26. The method of claim 25, wherein a third portionof the windings of the 3D inductor are formed by connections in at leastone metal layer of on a side of the substrate opposite the passiveportion.
 27. The method of claim 20, wherein the device is an integratedpassive device.
 28. The method of claim 20, wherein the magnetic coreextends beyond the windings of the 3D inductor.
 29. The method of claim20, wherein the magnetic core is at least one of iron (Fe), cobalt (Co)or nickel (Ni).